The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a method of providing an eDRAM (embedded dynamic random access memory) device using holes formed by using aspect ratio trapping structures (ART).
For more than three decades, the continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, further methods for improving performance in addition to scaling have become critical.
III-V CMOS is one high performance option for future technology nodes. III-V circuits need eDRAM as silicon CMOS does. Co-integration of III-V with silicon is very challenging due to the high lattice mismatch of III-V semiconductors and silicon. Aspect ratio trapping (ART) is one way to overcome the lattice mismatch, however ART requires trenches or pillars with dielectric, i.e., oxide or nitride sidewalls, to grow the III-V epitaxy. Those dielectric regions consume area, which is contrary to the shrinking requirements of future smaller device nodes.